1. Field of the Invention
The present invention relates to interface circuit arrangements in general and more particularly to interface circuit arrangements that connect I/O devices to data processing systems.
2. The Prior Art
Either a parallel communications network or a serial communications network has been used to provide communication between a data processing system and I/O terminals. Such I/O terminals may include displays, keyboards, scanners, etc. Most data processing systems and related I/O terminals differ in their designs and/or operation. In order to provide a somewhat standardized communications network an adapter is often used to capture and/or deliver data and other information to or from the communications network.
In the case of a parallel communications network the adapter is attached to a parallel data bus. When the I/O terminal is a display unit, data is read out of or written into a display random access memory (RAM) during a non-refreshed period (typically during horizontal and/or vertical retrace). Since this is an asynchronous event, relative to the bus timing, a read/write (R/W) control logic performs the synchronization necessary to get data into or out of the RAM during a non-display period. Although this technique works well for its intended purpose, it has several drawbacks including the fact that a multi-wire data bus is needed. Such multi-wire data buses are usually costly. In addition, the main engine or system microprocessor which places data on the multiplexor bus must wait for the adapter or be interrupted by it.
In the case of a serial communications network, a data format conversion circuit associated with each terminal is located at the parallel data processing system for converting parallel data to serial data and transmitting the serial data on a pair of lines running to each terminal. In most systems, two additional lines are used for carrying serial data from the terminals to the data processing system. The serial data is delivered to another data format conversion circuit which converts the serial data into parallel data. In this arrangement, at least two data format conversion circuits are needed at the central data processing system.
In an improvement aimed at reducing the component count of the prior art circuitry, U.S. Pat. No. 4,377,843 describes a data distribution interface in which a single data format conversion circuitry is used at the data processing system to effectuate parallel to serial conversion and vice versa.